An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems

Masayuki Sato, Takuya Toyoshima, Hikaru Takayashiki, Ryusuke Egawa, Hiroaki Kobayashi

Abstract


A modern memory system is equipped with many memory channels to obtain a high memory bandwidth. To take the advantage of this organization, applications’ data are distributed among the channels and transferred in an interleaved fashion. Although memory-intensive applications benefit from a high bandwidth by many memory channels, applications such as compute-intensive ones do not need the high bandwidth. To reduce the energy consumption for such applications, the memory system has low-power modes. During no memory request, the main memory can enter these modes and reduce energy consumption. However, these applications often cause intermittent memory requests to the channels that handle their data, resulting in not entering the low-power modes. Hence, the memory system cannot enter the low-power modes even though the applications do not need the high bandwidth. To solve this problem, this paper proposes a dynamic data allocation mechanism for many-channel memory systems. This mechanism forces data of such applications to use the specified channels by dynamically changing the address-mapping schemes and migrating the data. As a result, the other channels to which the data are not allocated can have a chance to enter the low-power modes for a long time. Therefore, the proposed mechanism has the potential to reduce the energy consumption of many-channel memory systems. The evaluation results show that this mechanism can reduce the energy consumption by up to 11.8% and 1.7% on average.


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References


Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M.D., Wood, D.A.: The gem5 simulator. ACM SIGARCH Computer Architecture News 39, 1–7 (Aug 2011), DOI: 10.1145/2024716.2024718

Bojnordi, M.N., Ipek, E.: Pardis: A programmable memory controller for the DDRx interfacing standards. In: 39th Annual International Symposium on Computer Architecture. pp. 13–24. IEEE, Portland, OR, USA (Jun 2012), DOI: 10.1109/ISCA.2012.6237002

Borkar, S.: Thousand core chips: A technology perspective. In: The 44th Annual Design Automation Conference. pp. 746–749. DAC ’07, ACM, New York, NY, USA (2007), DOI: 10.1145/1278480.1278667

Chatterjee, N., O0Connor, M., Lee, D., Johnson, D.R., Keckler, S.W., Rhu, M., Dally, W.J.: Architecting an energy-efficient DRAM system for GPUs. In: IEEE International Symposium on High Performance Computer Architecture (HPCA). pp. 73–84. Austin, TX, USA (2017), DOI: 10.1109/HPCA.2017.58

Eyerman, S., Eeckhout, L.: System-level performance metrics for multiprogram workloads. IEEE Micro 28(3), 42–53 (2008), DOI: 10.1109/MM.2008.44

Hur, I., Lin, C.: A comprehensive approach to DRAM power management. In: IEEE 14th International Symposium on High Performance Computer Architecture. pp. 305–316. Salt Lake City, UT, USA (Feb 2008), DOI: 10.1109/HPCA.2008.4658648

Jacob, B., Ng, S.W., Wang, D.T.: Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann (2008)

Jang, J.W., Jeon, M., Kim, H.S., Jo, H., Kim, J.S., Maeng, S.: Energy reduction in consolidated servers through memory-aware virtual machine scheduling. Computers, IEEE Transactions on 60(4), 552–564 (Apr 2011), DOI: 10.1109/TC.2010.82

Lebeck, A.R., Fan, X., Zeng, H., Ellis, C.: Power aware page allocation. ACM SIGOPS Operating Systems Review 34(5), 105–116 (Dec 2000), DOI: 10.1145/384264.379007

Li, S., Chen, K., Ahn, J.H., Brockman, J.B., Jouppi, N.P.: Cacti-p: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD). pp. 694–701. IEEE (Nov 2011), DOI: 10.1109/ICCAD.2011.6105405

Micron Technology Inc.: Micron MT40A2G4 data sheet (Oct 2015)

Sato, M., Chengguang, H., Komatsu, K., Egawa, R., Takizawa, H., Kobayashi, H.: An energy-efficient dynamic memory address mapping mechanism. In: IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII). pp. 1–3. Yokohama, Japan (Apr 2015), DOI: 10.1109/CoolChips.2015.7158660

Tran, K., Ahn, J.: HBM: Memory solution for high performance processors. In: MemCon. Santa Clara, CA, USA (Oct 2014)

Udipi, A.N., Muralimanohar, N., Chatterjee, N., Balasubramonian, R., Davis, A., Jouppi, N.P.: Rethinking DRAM design and organization for energy-constrained multi-cores. SIGARCH Comput. Archit. News 38(3), 175–186 (Jun 2010), DOI: 10.1145/1816038.1815983

Weis, C., Loi, I., Benini, L., Wehn, N.: Exploration and optimization of 3-D integrated DRAM subsystems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(4), 597–610 (Apr 2013), DOI: 10.1109/TCAD.2012.2235125

Wilkes, M.V.: The memory gap and the future of high performance memories. SIGARCH Comput. Archit. News 29(1), 2–7 (Mar 2001), DOI: 10.1145/373574.373576

Wu, D., He, B., Tang, X., Xu, J., Guo, M.: RAMZzz: Rank-aware DRAM power management with dynamic migrations and demotions. In: The International Conference on High Performance Computing, Networking, Storage and Analysis. pp. 32:1–32:11. Los Alamitos, CA, USA (Nov 2012), DOI: 10.5555/2388996.2389040

Wulf, W.A., McKee, S.A.: Hitting the memory wall: Implications of the obvious. ACM SIGARCH Computer Architecture News 23, 20–24 (Mar 1995), DOI: 10.1145/216585.216588

Yamada, Y.: Vector engine processor of NECs brand-new supercomputer SX-Aurora TSUBASA. In: HotChips: A Symposium on High Performance Chips. Cupertino, CA, USA (Aug 2018), https://www.hotchips.org/hc30/2conf/2.14_NEC_vector_NEC_SXAurora_TSUBASA_HotChips30_finalb.pdf




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